1. Field of the Invention
The present invention relates to a voltage detection circuit.
2. Description of the Related Art
Conventionally, in an integrated circuit (LSI), a voltage detection circuit is used for monitoring reduction of a power supply voltage, for example.
FIG. 3 is a block diagram showing an example of a configuration for monitoring reduction of a voltage. A logic circuit 100 has a CMOS inverter circuit, for example. A voltage VDD is applied to the logic circuit 100.
A voltage detection circuit 102 detects that the voltage VDD becomes lower than a predetermined voltage. If the voltage VDD becomes lower than a predetermined voltage, a logic operation of the logic circuit 100 is forced to be terminated, for example.
FIG. 4 is a diagram showing an example of a configuration of a CMOS interval circuit provided on the logic circuit 100, for example. The CMOS inverter circuit shown in FIG. 4 is provided with a P-channel type MOSFET (hereinafter, referred to as PMOS) MP and an N-channel type MOSFET (hereinafter, referred to as NMOS) MN connected serially between the voltage VDD and ground. A voltage VIN is applied to gates of the PMOS MP and the NMOS NM, and a voltage VOUT is output from a connection point of the PMOS MP and the NMOS NM.
In the CMOS inverter circuit with the configuration described above, assuming that VT (e.g., 0.85 V) is thresholds of the PMOS MP and the NMOS NM, if the voltage VDD becomes lower than 2*VT (1.7 V), the voltage VOUT may become high impedance.
FIG. 5 is a diagram for describing an operation of the CMOS inverter circuit when the voltage VDD<2*VT. A vertical axis is a voltage value of the voltage VIN. It is assumed that VT is thresholds of both the PMOS MP and the NMOS NM and that the voltage VDD is 1.5*VT.
In this case, when the voltage VIN is in the range of 1.5*VT>the voltage VIN>VT, the NMOS NM is turned on and the PMOS MP is turned off. Therefore, the voltage VOUT becomes “Low (hereinafter, referred to as L)”
When the voltage VIN is in the range of 0.5*VT>the voltage VIN>0, the NMOS NM is turned off and the PMOS MP is turned on. Therefore, the voltage VOUT becomes “High (hereinafter, referred to as H)”.
On the other hand, when the voltage VIN is in the range of VT>the voltage VIN>0.5*VT, both the NMOS NM and the PMOS MP are turned off. Therefore, the voltage VOUT becomes “Hi-z (high impedance)” and the operation of the CMOS inverter circuit becomes uncertain.
The voltage reduction of the voltage VDD increases the range of the voltage VIN which makes the voltage VOUT “Hi-z”. On the other hand, in the range of the voltage VDD>2*VT, the voltage VOUT does not become “Hi-z” regardless of the value of the voltage VIN.
Therefore, the voltage detection circuit 102 detects that the voltage VDD is reduced to, for example, 2*VT and, for example, terminates the operation of the CMOS inverter circuit if the voltage VDD becomes lower than 2*VT. In FIG. 3, if a plurality of voltages is used as the power supply voltage, a plurality of voltage detection circuits is provided correspondingly to each voltage.
As such a voltage detection circuit 102 detecting voltage reductions, propositions are made for voltage detection circuits which detect voltage reductions by using voltage dividing resistors and reference voltages See, e.g., Japanese Patent Application Laid-Open Publication No. 2002-296306.
FIG. 6 is a circuit diagram showing an example of a configuration of a conventional voltage detection circuit 102.
The voltage detection circuit 102 is provided with PMOS T1, T2, T3, T4 and T5, NMOS T6, T7 and T8, voltage dividing resistors R1 and R2, and a constant-current circuit I.
The voltage detection circuit shown in the figure is assumed to detect that a voltage VDD becomes lower than 2*VT (1.7 V) described above.
A voltage VCC is applied to sources of the PMOS T1, T2 and T3; gates of the PMOS T1, T2 and T3 are mutually connected; and a drain of the diode-connected PMOS T1 is connected to the constant-current circuit I. The diode connection is to short-circuit a gate and a drain in the case of the MOSFET and to short-circuit a base and a collector in the case of a bipolar transistor. Such a diode-connected transistor performs the same operation as a diode element in PN junction.
The PMOS T1, T2 and T3 constitute a current mirror circuit, and if the PMOS T1, T2 and T3 have a transistor size ratio of 1, constant currents flowing through the PMOS T2 and the PMOS T3 are the same level as a current I flowing through the PMOS T1.
A source of the PMOS T4 is connected to a drain of the PMOS T2 and a drain of the PMOS T4 is connected to a drain of the NMOS T6. A voltage applied to a gate of the PMOS T4 is the voltage VDD divided by the resistor R1 and the resistor R2, i.e., the voltage VDD×R2/(R1+R2). R1 and R2 are resistance values of the resistor R1 and the resistor R2, and when assuming that a ratio of R1 to R2 is, for example, 5:12 and if the voltage VDD is 1.7V, a gate voltage of the PMOS T4 is 1.2V.
A source of the PMOS T5 is connected to the drain of the PMOS T2 and a drain of the PMOS T5 is connected to a drain of the NMOS T7. A reference voltage VREF (e.g., 1.2 V) is generated by a reference voltage generation circuit and applied to a gate of the PMOS T5.
Sources of both the NMOS T6 and the NMOS T7 are grounded and the NMOS T6 is a diode-connected current mirror circuit. Therefore, if the NMOS T6 and the NMOS T7 have a transistor size ratio of 1, a constant current flowing through the NMOS T7 is the same level as a drain current of the NMOS T6.
A drain of the NMOS T8 is connected to a drain of the PMOS T3 as well as a detection-result output terminal. A source of the NMOS T8 is grounded. A gate of the NMOS T8 is connected to a drain of the PMOS T5. The NMOS T8 is assumed to have a transistor size ratio greater than the PMOS T3.
Then, descriptions are made for the operation of the voltage detection circuit shown in FIG. 6.
The constant current I is always applied to the drains of the PMOS T1, T2 and T3 constituting a current mirror circuit. Since the sources of the PMOS T4 and the PMOS T5 are connected in common, the sum of the currents applied to the PMOS T4 and the PMOS T5 is I. In other words, a relationship is established as Ia+Ib=I.
If the voltage VDD is larger than 1.7 V, that is, if the gate voltage of the PMOS T4 is larger than the gate voltage of the PMOS T5, a current Ia flowing between the source and drain of the PMOS T4 is smaller than a current Ib flowing between the source and drain of the PMOS T5. Therefore, a current Ib−Ia is supplied to a base of the NMOS T8 and the NMOS T8 is turned on. Since a voltage of detection-result output terminal is reduced, the output of the detection-result output terminal becomes “L”.
On the other hand, if the voltage VDD is smaller than 1.7 V, that is, if the gate voltage of the PMOS T4 is larger than the gate voltage of the PMOS T5, the current Ia flowing between the source and drain of the PMOS T4 is larger than the current Ib flowing between the source and drain of the PMOS T5. Also, the NMOS T6 and T7 in the current mirror connection attempt to apply the current Ia between the drain and source. Since the current Ia is larger than the current Ib, a current is not supplied to the gate of the NMOS T8 and the NMOS T8 is turned off. Therefore, since the constant current I is supplied from the PMOS T3 to the detection-result output terminal and the voltage of the detection-result output terminal becomes high, the output of the detection-result output terminal becomes “H”.
Therefore, the voltage detection circuit 102 can detect that the power supply voltage VDD becomes lower than 2*VT (1.7V) since the output of the detection-result output terminal changes from “L” to “H”.
In this way, the conventional voltage detection circuit detects that the voltage VDD becomes lower than, for example, 2*VT, using the voltage dividing resistor dividing the voltage VDD and the reference voltage VREF from the reference voltage generation circuit.
In order to detect reduction of a voltage VDD, A conventional voltage detection circuit 102 shown in FIG. 6 needs resistors R1 and R2 dividing the voltage VDD and a reference voltage VREF obtained from a reference voltage generation circuit provided outside of the voltage detection circuit 102, besides MOSFET.
Also, when performing the voltage detection, since it is decided whether a voltage is larger or smaller than the reference voltage VREF by applying currents to the voltage dividing resistors R1 and R2, it is problematic that power consumption is increased.
Further, if the reference voltage generation circuit is included and integrated onto the same chip, it is problematic that a chip area is increased.